Տեղեկատվական տեխնոլոգիաների կրթական եւ հետազոտական կենտրոն
YSU Information Technologies Educational and Research Center
Established in 2007, IT Educational and Research Center (IT ERC) serves as an interdisciplinary hub for educational program. Headed by Prof. Samvel K. Shoukourian:
>
Gurgen E. Harutyunyan

Assistant | Chair of Information Systems
Education
2005 - 2008: Yerevan State University, Faculty of Informatics and Applied Mathematics, PhD in technical sciences
2003 - 2005: Yerevan State University, Faculty of Informatics and Applied Mathematics, Master degree
1999 - 2003: Yerevan State University, Faculty of Informatics and Applied Mathematics, Bachelor degree
1998 - 1999: College of city Abovyan
1994 - 1998: School N2, city Abovyan
1989 - 1994: School N10, city Abovyan
PhD in technical sciences, 2008, Yerevan State University

Work Experience
2010 - 2012: Synopsys, Senior engineer
2004 - 2010: Virage Logic, Senior engineer
2000 - 2004: Yerevan State University, programmer

Research interest
Testing memory devices
The list of scientific works is attached

Awards
TTTC/ITC Commemorative Gerald W. Gordon Award for Student Volunteer Service, International Test Conference (ITC), USA, 2008
Best student presentation in IEEE East-West Design and Test Workshop, Russia, 2006

Languages
Armenian, Russian, English

Latest Publications (47)
G. Harutyunyan , S. Martirosyan, S. Shoukourian , Y. Zorian
Memory Physical Aware Multi-Level Fault Diagnosis Flow
2020 | Article
IEEE Transactions on Emerging Topics in Computing, VOLUME 8, NO. 3, JULY-SEPT. 2020, pp.700-711
Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism
2019 | Article
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019, Volume 38, Number 3, 562-575 էջ
Hayk Grigoryan, Grigor Tshagharyan, Gurgen Harutyunyan , Samvel Shoukourian , Samvel Shoukourian, Yervant Zorian
DETECTION OF ADDRESS ERRORS IN MEMORY DEVICES USING MULTI-SEGMENT ERROR DETECTION CODES
2019 | Patent
Patent No.: US 11/023,310, Date of Patent: June 1, 2021, Appl. No. 16/549,419, filed on August 23, 2019.

Hayk Grigoryan, Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
Security Issues in Test and Repair Infrastructure for Systems-on-Chip
2017 | Article
Информационно-коммуникационные технологии в науке, производстве и образовании ICIT-2017. 2017, стр. 114-122
|
Testing electronic memories based on fault and test algorithm periodicity
2017 | Patent
SYNOPSYS, INC. (Mountain View, CA). 9831000. Nov 28, 2017
D. Sargsyan, Gurgen Harutyunyan , Samvel K. Shoukourian , Yervant Zorian
Automated flow for test pattern creation for IPs in SoC
2017 | Article
EWDTS. 2017: 21-24 pp
|
S. Martirosyan, Gurgen Harutyunyan , Samvel K. Shoukourian , Yervant Zorian
An efficient testing methodology for embedded flash memories
2017 | Article
EWDTS. 2017: 422-425 pp
|
G. Tshagharyan, Gurgen Harutyunyan , Samvel K. Shoukourian , Yervant Zorian
Experimental study on Hamming and Hsiao codes in the context of embedded applications
2016 | Article
EWDTS, 2017: 25-28 pp.
|
Lusine Martirosyan, Gurgen Harutyunyan , Samvel K. Shoukourian , Yervant Zorian
A power based memory BIST grouping methodology
2015 | Article
East-West Design & Test Symposium (EWDTS). 2015, p. 27-30
|
Grigor Tshagharyan, Gurgen Harutyunyan , Samvel K. Shoukourian , Yervant Zorian
Overview study on fault modeling and test methodology development for FinFET-based memories
2015 | Article
East-West Design & Test Symposium (EWDTS). 2015, p. 19-22
|
Grigor Tshagharyan, Gurgen Harutyunyan , Samvel K. Shoukourian , Yervant Zorian
Overview study on fault modeling and test methodology development for FinFET-based memories
2015 | Article
East-West Design & Test Symposium (EWDTS), Batumi, Georgia September 26-29, 2015, pp. 5-9 (english)
Lusine Martirosyan, Gurgen Harutyunyan , Samvel K. Shoukourian , Yervant Zorian
A power based memory BIST grouping methodology
2015 | Article
East-West Design and Test Symposium (EWDTS), Batumi, Georgia September 26-29, 2015, pp. 11-15 (english)
Extending fault periodicity table for testing faults in memories under 20nm
2014 | Article
East-West Design & Test Symposium (EWDTS), Kiev, Ukraine September 26-29, 2014, pp. 5 - 9 (english)
“An Efficient Fault Diagnosis and Localization Algorithm for Successive-Approximation Analog to Digital Converters''
2012 | Article
Proc. IEEE East-West Design and Test Symposium, Kharkov National University of Radioelectronics, Kharkov, Ukraine, Sep. 14-17, 2012, pp. 15-18
“A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs”
2012 | Article
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 31, Number 6, June 2012, pp. 941-949
M. HG, J. Shah, H. Chukhajyan, G. Harutyunyan
“TCAM BIST Methodology and Test Scheme”
2012 | Article
Synopsys Users Group Conference (SNUG), India, 2012
“Fault and Test Algorithm Periodicity Hypothesis in Memory Devices and Its Application to Memory BIST Processor Architecture”
2012 | Article
Reports of National Academy of Sciences of Armenia, 2012, Vol. 112, No. 3, pp. 229-238
"An Efficient Fault Diagnosis and Localization Algorithm for Successive-Approximation Analog to Digital Converters"
2012 | Article
IEEE East-West Design and Test Symposium (EWDTS), Ukraine, 2012, pp. 15-18
K. Amirkhanyan, A. Davtyan, G. Harutyunyan , T. Melkumyan, S. Shoukourian , V. Vardanian , Y. Zorian
"Application of Defect Injection Flow for Fault Validation in Memories"
2012 | Article
IEEE East-West Design and Test Symposium (EWDTS), Ukraine, 2012, pp. 19-22
Karen Amirkhanyan, Karen Darbinyan, Arman Davtyan, Gurgen Harutyunyan , Samvel Shoukourian , Valery Vardanian , Yervant Zorian
“GENERATION OF MEMORY STRUCTURAL MODEL BASED ON MEMORY LAYOUT”
2012 | Article
No. 13/531,189, Filing date – June 22, 2012
“Generic BIST Architecture for Testing of Content Addressable Memories”
2011 | Article
IEEE International On-Line Testing Symposium (IOLTS), Greece, 2011, pp. 86-91
“Implementation of a Flexible BIST Architecture Based on Programmability of Test Operations, Patterns and Algorithms”
2011 | Article
Computer Science and Information Technologies (CSIT), Armenia, 2011, pp. 287-290
“A Robust Solution for Embedded Memory Test and Repair”
2011 | Article
IEEE Asian Test Symposium (ATS), India, 2011, pp. 461-462
“Symmetry Measure for Memory Test and Its Application in BIST Optimization”
2011 | Article
Journal of Electronic Testing: Theory and Applications (JETTA), Volume 27, Number 6, December 2011, pp. 753-766
“TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIODICITY”
2011 | Article
No. 13/183,468, Filing date - July 15, 2011
Karen Amirkhanyan, Hayk Grigoryan, Gurgen Harutyunyan , Tatevik Melkumyan, Samvel Shoukourian , Alex Shubat, Valery Vardanian , Yervant Zorian
“DETECTING RANDOM TELEGRAPH NOISE INDUCED FAILURES IN AN ELECTRONIC MEMORY”
2011 | Article
No. 13/183,471, Filing date - July 15, 2011
“DETERMINING A DESIRABLE NUMBER OF SEGMENTS FOR A MULTI-SEGMENT SINGLE ERROR CORRECTING CODING SCHEME”
2011 | Article
No. 13/310,479, Filing date – December 2, 2011
“Minimal Algorithms for Testing Content-Addressable Memories”
2010 | Thesis
In proc. of IEEE East-West Design & Test Symposium 2010, St. Petersburg, Russia, September 17-20, 2010
“Minimal March Test Algorithms for Detection of All Realistic Two-Operation, Two-Cell Dynamic Faults from Subclasses Sav and Sva”
2010 | Article
Reports of National Academy of Sciences of Armenia, 2010, Vol. 110, No. 2, pp. 143-150
G. E. Harutyunyan , D. V. Melkumyan
“Fault Location and Diagnosis Algorithm for Static and Dynamic Faults in SRAMs”
2010 | Article
Proceedings of the National Academy of Sciences of Armenia and the State Engineering University of Armenia. Series of Technical Sciences, 2010, Vol. 63, No. 3, pp. 280-287
H. Avetisyan, G. Harutyunyan , V.A. Vardanian , Y. Zorian
“An Efficient March Test for Detection of All Two-Operation Dynamic Faults from Subclass Sav”
2009 | Article
IEEE East-West Design and Test Symposium (EWDTS), Russia, 2009, pp. 175-178
“An Efficient March Test Algorithm for Detection of Resistive Shorts in Multi-Port SRAMs”
2009 | Article
Computer Science and Information Technologies (CSIT), Armenia, 2009, pp. 435-438
“An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories”
2008 | Article
IEEE VLSI Test Symposium (VTS), USA, 2008, pp. 95 – 100
G. Harutunyan , D. Melkumyan, H. Elchyan, V. Vardanian
“An Efficient Method for Generation of March Tests Based on Formulas”
2008 | Article
Mathematical problems of cybernetics and computer science, Armenia, 2008, pp. 5-17
“Efficient March-Like Algorithm for Detection of All Two-Operation Dynamic Faults from Subclass Sav”,
2008 | Article
Mathematical problems of cybernetics and computer science, Armenia, 2008, pp. 18-24
“Minimal March Tests for Detection of Dynamic Faults in Random Access Memories”
2007 | Article
Journal of Electronic Testing: Theory and Applications (JETTA), Volume 23, Number 1, February 2007, pp. 55-74
"A March-Based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories”
2007 | Article
IEEE Design and Diagnosis of Electronic Circuits and Systems (DDECS), Poland, 2007, pp. 145-148
“Minimal March Tests for Dynamic Faults in Random Access Memories”
2007 | Article
IEEE European Test Symposium (ETS), Germany, 2007, pp. 223 – 227
“An Efficient 2-Phase March Algorithm for Full Diagnosis of All Simple Static Faults in Random Access Memories”
2007 | Article
IEEE East-West Design and Test Symposium (EWDTS), Armenia, 2007, pp. 110-113
“A Software Tool for Generation of March Algorithms for Faults in SRAMs”
2007 | Article
IEEE East-West Design and Test Symposium (EWDTS), Armenia, 2007, pp. 444-447
”Minimal March-Based Fault Location Algorithm with Partial Diagnosis for All Static Faults in Random Access Memories”
2006 | Article
IEEE Design and Diagnosis of Electronic Circuits and Systems (DDECS), Czech Republic, 2006, pp. 260-265
Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories”
2006 | Article
IEEE VLSI Test Symposium (VTS), USA, 2006, pp. 120-125
“Minimal March Tests for Dynamic Faults in Random Access Memories”
2006 | Article
IEEE European Test Symposium (ETS), UK, 2006, pp. 43-48
“A March Based Algorithm for Location and Full Diagnosis of All Unlinked Static Faults”
2006 | Article
IEEE Memory Technology, Design and Testing (MTDT), Taiwan, 2006, pp 9-14
“A March Test for Full Diagnosis of All Simple Static Faults in Random Access Memories”
2006 | Article
IEEE East-West Design and Test Workshop (EWDTW), Russia, 2006, pp. 68-71
“Minimal March Tests for Unlinked Static Faults in Random Access Memories”
2005 | Article
IEEE VLSI Test Symposium (VTS), USA, 2005, pp. 53-59
Minimal March-Based Fault Location Algorithm with Partial Diagnosis for Random Access Memories”
2005 | Article
Computer Science and Information Technologies (CSIT), Armenia, 2005, pp. 519-522