Տեղեկատվական տեխնոլոգիաների կրթական եւ հետազոտական կենտրոն
YSU Information Technologies Educational and Research Center
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Polynomial algorithm for equivalence problem of deterministic multitape finite automata
2020 | Հոդված
Theoretical Computer Science, Volume 833C, 2020, Pages 120-132
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Memory Physical Aware Multi-Level Fault Diagnosis Flow
2020 | Հոդված
IEEE Transactions on Emerging Topics in Computing, VOLUME 8, NO. 3, JULY-SEPT. 2020, pp.700-711
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Finfet-Based Memory Testing Using Multiple Read Operations
2019 |
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Armenia: Communicating to World Community in Electronic Test and Design
2019 | Հոդված
ITC 2019: IEEE International Test Conference, 2019, 1-3 էջ
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Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism
2019 | Հոդված
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019, Volume 38, Number 3, 562-575 էջ
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DETECTION OF ADDRESS ERRORS IN MEMORY DEVICES USING MULTI-SEGMENT ERROR DETECTION CODES
2019 |
Patent No.: US 11/023,310, Date of Patent: June 1, 2021, Appl. No. 16/549,419, filed on August 23, 2019.

Hayk Grigoryan, Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
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Armenia: Communicating to World Community in Electronic Test and Design
2019 | Հոդված
ITC 2019: 1-3, IEEE International Test Conference, 2019-11-12, 2019-11-14, Վաշինգտոն
Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism
2019 | Հոդված
IEEE, Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 38, No 3, 2019, pp. 562-575
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Security Issues in Test and Repair Infrastructure for Systems-on-Chip
2017 | Հոդված
Информационно-коммуникационные технологии в науке, производстве и образовании ICIT-2017. 2017, стр. 114-122
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Testing electronic memories based on fault and test algorithm periodicity
2017 |
SYNOPSYS, INC. (Mountain View, CA). 9831000. Nov 28, 2017
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Automated flow for test pattern creation for IPs in SoC
2017 | Հոդված
EWDTS. 2017: 21-24 pp
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An efficient testing methodology for embedded flash memories
2017 | Հոդված
EWDTS. 2017: 422-425 pp
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Experimental study on Hamming and Hsiao codes in the context of embedded applications
2016 | Հոդված
EWDTS, 2017: 25-28 pp.
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A power based memory BIST grouping methodology
2015 | Հոդված
East-West Design & Test Symposium (EWDTS). 2015, p. 27-30
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Overview study on fault modeling and test methodology development for FinFET-based memories
2015 | Հոդված
East-West Design & Test Symposium (EWDTS). 2015, p. 19-22
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Overview study on fault modeling and test methodology development for FinFET-based memories
2015 | Հոդված
East-West Design & Test Symposium (EWDTS), Batumi, Georgia September 26-29, 2015, pp. 5-9 (english)
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An efficient approach for memory repair by reducing the number of spares
2015 | Հոդված
East-West Design & Test Symposium (EWDTS) Batumi, Georgia September 26-29, 2015, pp. 21-25 (english)
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A power based memory BIST grouping methodology
2015 | Հոդված
East-West Design and Test Symposium (EWDTS), Batumi, Georgia September 26-29, 2015, pp. 11-15 (english)
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Extending fault periodicity table for testing faults in memories under 20nm
2014 | Հոդված
East-West Design & Test Symposium (EWDTS), Kiev, Ukraine September 26-29, 2014, pp. 5 - 9 (english)
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“An Efficient Fault Diagnosis and Localization Algorithm for Successive-Approximation Analog to Digital Converters''
2012 | Հոդված
Proc. IEEE East-West Design and Test Symposium, Kharkov National University of Radioelectronics, Kharkov, Ukraine, Sep. 14-17, 2012, pp. 15-18
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“Various methods and apparatuses for memory modeling using a structural primitive verification for memory compilers”
2012 |
US Patent No. 8,112,730, 2012
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Instrumental Environment of Virtual Learning of Yerevan State University and its Application
2012 | Հոդված
In Proc. of the Status and Prospects of the Development of Professional Retraining and Advanced Training of Specialists in the New NIS Countries Along New Directions Development Technics and Technologies, Moscow, Russia, 2012, pp. 55-60. (Russian)
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“A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs”
2012 | Հոդված
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 31, Number 6, June 2012, pp. 941-949
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“Fault and Test Algorithm Periodicity Hypothesis in Memory Devices and Its Application to Memory BIST Processor Architecture”
2012 | Հոդված
Reports of National Academy of Sciences of Armenia, 2012, Vol. 112, No. 3, pp. 229-238
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"An Efficient Fault Diagnosis and Localization Algorithm for Successive-Approximation Analog to Digital Converters"
2012 | Հոդված
IEEE East-West Design and Test Symposium (EWDTS), Ukraine, 2012, pp. 15-18
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"Application of Defect Injection Flow for Fault Validation in Memories"
2012 | Հոդված
IEEE East-West Design and Test Symposium (EWDTS), Ukraine, 2012, pp. 19-22
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“GENERATION OF MEMORY STRUCTURAL MODEL BASED ON MEMORY LAYOUT”
2012 | Հոդված
No. 13/531,189, Filing date – June 22, 2012
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“Generic BIST Architecture for Testing of Content Addressable Memories”
2011 | Հոդված
IEEE International On-Line Testing Symposium (IOLTS), Greece, 2011, pp. 86-91
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“A Robust Solution for Embedded Memory Test and Repair”
2011 | Հոդված
IEEE Asian Test Symposium (ATS), India, 2011, pp. 461-462
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“Symmetry Measure for Memory Test and Its Application in BIST Optimization”
2011 | Հոդված
Journal of Electronic Testing: Theory and Applications (JETTA), Volume 27, Number 6, December 2011, pp. 753-766
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“TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIODICITY”
2011 | Հոդված
No. 13/183,468, Filing date - July 15, 2011
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“DETECTING RANDOM TELEGRAPH NOISE INDUCED FAILURES IN AN ELECTRONIC MEMORY”
2011 | Հոդված
No. 13/183,471, Filing date - July 15, 2011
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“DETERMINING A DESIRABLE NUMBER OF SEGMENTS FOR A MULTI-SEGMENT SINGLE ERROR CORRECTING CODING SCHEME”
2011 | Հոդված
No. 13/310,479, Filing date – December 2, 2011
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The Equivalence Problem of Deterministic Multitape Finite Automata: A New Proof of Solvability Using a Multidimensional Tape
2010 | Հոդված
Proceedings of LATA 2010: Language and Automata Theory and Applications, 4th International Conference, Trier, Germany, May 24-28, 2010, Lecture Notes in Computer Science, 6031, Springer 2010,: 392-402
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“Minimal Algorithms for Testing Content-Addressable Memories”
2010 |
In proc. of IEEE East-West Design & Test Symposium 2010, St. Petersburg, Russia, September 17-20, 2010
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“Memory Modeling Using an Intermediate Level Structural Description”
2010 | Հոդված
US Patent, No 7768840, USA, 2010
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Solvability of Formal Verification Problem for Business Process Templates
2010 | Հոդված
Published in Proceedings of Emerging M&S Applications in Industry and Academia Symposium 2010 (EAIA 2010), SpringSim’2010 Multi-conference of Society for Computer Simulation, pp. 66-74, 11-15 April 2010, Orlando, FL, USA
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An approach for formal verification of business processes
2009 | Հոդված
In Proceedings of the 2009 Spring Simulation Multiconference, SpringSim 2009
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An Approach for Formal Verification of Business Processes
2009 | Հոդված
Published in Business and Industry Symposium 2009 (BIS'09), SpringSim'09 Multi-conference of Society for Computer Simulation, ACM Press, March 2009, San Diego, USA
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Process Based Management of Specific GRID Configurations: Verification of Changes"
2009 | Հոդված
Published in Proceedings of "The Future Business Technology Conference" (FUBUTEC'2009), EUROSIS, pp. 57-61, April 2009, Bruges, Belgium
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The Equivalence Problem of Multidimensional Multitape Automata
2008 | Հոդված
Journal of Computer and System Sciences Volume 74, Issue 7, November 2008, Pages 1131-1138, Copyright 2008 Elsevier Inc
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“Tuning Of IT Management Processes To A Computing Grid”
2008 | Հոդված
In Proceedings of GRID’2008, Distributed Computing And GRID Technologies In Education And Science International Conference GRID’2008, Dubna, Russian Federation, 2008. pp. 71-74
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The Equivalence of 2-dimensional Multitape Automata
2008 |
Cybernetics and Systems Analysis, Number 1, 2008
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Hierarchical Silicon Aware Test and Repair IP: Development and Integration Flow Reducing Time to Market for Systems on Chip
2006 |
Invited paper, 4th IEEE East-West Design and Test Workshop, Sochi, Russia, September 2006
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SoC yield optimization via an embedded memory test and repair infrastructure
2004 | Հոդված
IEEE Design & Test of Computers, vol.21, May-June, 2004, pp. 200-207
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A methodology for design and evaluation of redundancy allocation algorithms
2004 | Հոդված
Proc. IEEE VLSI Test Symposium, Napa Valley, USA, 2004, pp. 249-255
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Embedded Memory Test & Repair: Infrastructure IP for SOC Yield
2003 | Հոդված
IEEE Design and Test of Computers, May-June, 2003, pp.58-66
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A bridge between two models of processes for distributed systems
2003 |
Proceedings of BISINESS SIMULATION‘2003, SCS International Advanced Simulation Technologies Conference ASTC’2003, Orlando, USA, April 2003
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Determination of critical paths for hammock type processes
2003 |
Proceedings of HIGH PERFORMANCE COMPUTING‘2003, SCS International Advanced Simulation Technologies Conference ASTC’2003, Orlando, USA, April 2003
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Verification of hammock type processes
2003 | Հոդված
Proceedings of DESIGN AND ANALYSIS OF DISTRIBUTED SYSTEMS‘2003, SCS International Advanced Simulation Technologies Conference ASTC’2003, Orlando, USA, April 2003
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Embedded memory test, debug and repair using CTL
2002 |
Embedded Tutorial at European Test Workshop, May 2002, Corfu, Greece
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An approach for CTL implementation
2002 | Հոդված
Proceedings of IEEE 6th International Workshop on Testing of Embedded Core Systems, Monterey, USA, pp. 43-49, May 2002
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Transformation of hammock type processes
2002 | Հոդված
Proceedings of HIGH PERFORMANCE COMPUTING‘2002, SCS International Advanced Simulation Technologies Conference ASTC’2002, San Diego, USA, pp. 288-293, April 2002
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‘An approach for evaluation of redundancy analysis algorithms’
2001 | Հոդված
Records of IEEE Int. Workshop on Memory Technology, Design and Testing’, MTDT’01, San Jose, USA, pp. 51-55, 2001
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Tuning of multicomputers to specific tasks
2000 | Հոդված
A Review, Proceedings of Yerevan State University, Yerevan, Armenia, , pp. 34-40, October-December 2000
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Design of reliable testing systems via feeble testers
2000 | Հոդված
A model and applications, Digest of papers, IEEE 4th International Workshop on System Test and Diagnosis, Atlantic City, USA, pp. 83-91, October 2000
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Combination of separate processes in a distributed environment
2000 | Հոդված
A case of study, Proceedings of HIGH PERFORMANCE COMPUTING‘2000, SCS International Advanced Simulation Technologies Conference ASTC’2000, USA, , pp. 280-285, April 2000
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Tuning the architecture of multi-computers to specific algorithms
1999 | Հոդված
Proceedings of Joint Workshop of Iowa State University (USA) and Institute for Informatics and Automation Problems of NAS (Armenia), August 1999, Yerevan, Armenia
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An approach for access differentiation design in medical distributed applications built on databases
1999 | Հոդված
Proceedings of 15th European Congress on Medical Informatics, MIE ’99, Ljubljana, Slovenia, pp. 392-397, August 1999
A unified design methodology for off-line and on-line testing
1998 | Հոդված
IEEE Design and Test of Computers, pp. 73-79, April-June, 1998
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Designing a virtual operating room for prediction of operative interventions under some pathologies of middle ear
1998 |
A case of the database, Proceedings of 9th World Congress on Medical Informatics, Medinfo ’98, Seoul, Korea, August 1998
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Fast algorithms of tuning computer systems based on a concurrent network architecture
1998 | Հոդված
Proceedings of HIGH PERFORMANCE COMPUTING ‘98, SCS International Advanced Simulation Technologies Conference ASTC’98, Boston, USA, pp.163-167, April 1998
Results on Justification of a Unified Test Design Technology both for Offline and Online Testing
1997 | Հոդված
Proc. of the Conf. Computer Science & Information Technologies, Yerevan, Armenia, 1997, pp. 326-329
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Implementation of algorithms on computer systems using a concurrent network architecture
1996 | Հոդված
HIGH PERFORMANCE COMPUTING ‘96, “Grand Challenges in Computer Simulation” Proceedings of SCS International Simulation Multiconference, New Orleans, USA, pp. 302-307, 1996
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An Approach for System Tests Design and Its Applications
1995 | Հոդված
Proc. of the 13-th IEEE VLSI Test Symposium, NJ, Princeton, USA, 1995, pp. 448-453
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Dynamic adaptation system for EC1170 computer
1991 | Հոդված
Voprosy radioelectroniki, seriya EVT, 10:12-15, 1991
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A control program for multicomputer complex testing
1990 | Հոդված
Voprosy radioelectroniki, seriya EVT, 11:31-37, 1990
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Software tools for automatic generation of microcode assists for EC1046 Computer
1989 | Հոդված
Voprosy radioelectroniki, seriya EVT, 12:54-56,1989
An approach for microcode assists synthesis problem
1989 | Հոդված
Kibernetika, 4:26-32, 1989.(translated into English in USA)
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Adaptation to applications in EC1046 computer via microprogramming
1988 | Հոդված
Vychislitelnaya tekchnika socialisticheskikch stran, 23:45-48, 1988
Principles of microprogram adaptation to a given workload for mainframe type computers
1988 | Հոդված
Proceedings of Radioindustry ministry conference on computers, 1988, 103-105
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Dynamic microprogramming in functional tests design for the EC type computers
1987 | Հոդված
Proceedings of All-Union conference on computers, 1987, 134-135
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Peculiarities of dynamic microprogramming and engineering assists implementation in EC1046 computer
1986 | Հոդված
Voprosy radioelectroniki, seriya EVT, 11: 3-10, 1986
Engineering assists in EC1046 computer
1984 | Հոդված
Voprosy radioelectroniki, seriya EVT, 6:92-99, 1984
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A tool for analyzing the completeness of functional tests
1983 | Հոդված
Proceedings of All-Union conference on computer aided design, 1983, 231-232
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APL dialogue system
1983 | Հոդված
Voprosy radioelectroniki, seriya EVT, 8: 51-59, 1983
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Emulation of an APL machine on EC1045 computer
1981 | Հոդված
Voprosy radioelectroniki, seriya EVT, 16:19-27, 1981
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On a reducibility of the equivalence problem for program schemata in a rank 1 nontrivial basis to the equivalence problem for multidimensional multihead automata
1980 | Հոդված
Kibernetika, 6:1-7, 1980 (translated into English in USA)
A result on the functional equivalence problem for program schemata in a rank 1 nontrivial basis
1979 | Հոդված
Programmirovanie, 2:41-49, 1979
A practical method for recognizing the equivalence of algorithms
1977 | Հոդված
Voprosy radioelectroniki, seriya EVT, 12:8-12, 1977
On the execution time comparison for two-way automata and the equivalence problem for a class of discrete processors and program schemata
1977 | Հոդված
Kibernetika, 2:9-14, 1977 (translated into English in USA)
On some solvable cases of the equivalence problem for X-Y-automata
1976 | Հոդված
Doklady AN Arm. SSR, 1:27-32, 1976 (translated into English in USA)
The equivalence problem for a class of multitape multihead automata and program schemata
1976 | Հոդված
Kibernetika, 4:12-16, 1976 (translated into English in USA)