Տեղեկատվական տեխնոլոգիաների կրթական եւ հետազոտական կենտրոն
YSU Information Technologies Educational and Research Center
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Последние публикации (47)
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Memory Physical Aware Multi-Level Fault Diagnosis Flow
2020 | Հոդված
IEEE Transactions on Emerging Topics in Computing, VOLUME 8, NO. 3, JULY-SEPT. 2020, pp.700-711
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Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism
2019 | Հոդված
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019, Volume 38, Number 3, 562-575 էջ
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DETECTION OF ADDRESS ERRORS IN MEMORY DEVICES USING MULTI-SEGMENT ERROR DETECTION CODES
2019 |
Patent No.: US 11/023,310, Date of Patent: June 1, 2021, Appl. No. 16/549,419, filed on August 23, 2019.

Hayk Grigoryan, Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
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Security Issues in Test and Repair Infrastructure for Systems-on-Chip
2017 | Հոդված
Информационно-коммуникационные технологии в науке, производстве и образовании ICIT-2017. 2017, стр. 114-122
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Testing electronic memories based on fault and test algorithm periodicity
2017 |
SYNOPSYS, INC. (Mountain View, CA). 9831000. Nov 28, 2017
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Automated flow for test pattern creation for IPs in SoC
2017 | Հոդված
EWDTS. 2017: 21-24 pp
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An efficient testing methodology for embedded flash memories
2017 | Հոդված
EWDTS. 2017: 422-425 pp
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Experimental study on Hamming and Hsiao codes in the context of embedded applications
2016 | Հոդված
EWDTS, 2017: 25-28 pp.
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A power based memory BIST grouping methodology
2015 | Հոդված
East-West Design & Test Symposium (EWDTS). 2015, p. 27-30
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Overview study on fault modeling and test methodology development for FinFET-based memories
2015 | Հոդված
East-West Design & Test Symposium (EWDTS). 2015, p. 19-22
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Overview study on fault modeling and test methodology development for FinFET-based memories
2015 | Հոդված
East-West Design & Test Symposium (EWDTS), Batumi, Georgia September 26-29, 2015, pp. 5-9 (english)
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A power based memory BIST grouping methodology
2015 | Հոդված
East-West Design and Test Symposium (EWDTS), Batumi, Georgia September 26-29, 2015, pp. 11-15 (english)
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Extending fault periodicity table for testing faults in memories under 20nm
2014 | Հոդված
East-West Design & Test Symposium (EWDTS), Kiev, Ukraine September 26-29, 2014, pp. 5 - 9 (english)
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“An Efficient Fault Diagnosis and Localization Algorithm for Successive-Approximation Analog to Digital Converters''
2012 | Հոդված
Proc. IEEE East-West Design and Test Symposium, Kharkov National University of Radioelectronics, Kharkov, Ukraine, Sep. 14-17, 2012, pp. 15-18
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“A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs”
2012 | Հոդված
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 31, Number 6, June 2012, pp. 941-949
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“TCAM BIST Methodology and Test Scheme”
2012 | Հոդված
Synopsys Users Group Conference (SNUG), India, 2012
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“Fault and Test Algorithm Periodicity Hypothesis in Memory Devices and Its Application to Memory BIST Processor Architecture”
2012 | Հոդված
Reports of National Academy of Sciences of Armenia, 2012, Vol. 112, No. 3, pp. 229-238
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"An Efficient Fault Diagnosis and Localization Algorithm for Successive-Approximation Analog to Digital Converters"
2012 | Հոդված
IEEE East-West Design and Test Symposium (EWDTS), Ukraine, 2012, pp. 15-18
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"Application of Defect Injection Flow for Fault Validation in Memories"
2012 | Հոդված
IEEE East-West Design and Test Symposium (EWDTS), Ukraine, 2012, pp. 19-22
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“GENERATION OF MEMORY STRUCTURAL MODEL BASED ON MEMORY LAYOUT”
2012 | Հոդված
No. 13/531,189, Filing date – June 22, 2012
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“Generic BIST Architecture for Testing of Content Addressable Memories”
2011 | Հոդված
IEEE International On-Line Testing Symposium (IOLTS), Greece, 2011, pp. 86-91
“Implementation of a Flexible BIST Architecture Based on Programmability of Test Operations, Patterns and Algorithms”
2011 | Հոդված
Computer Science and Information Technologies (CSIT), Armenia, 2011, pp. 287-290
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“A Robust Solution for Embedded Memory Test and Repair”
2011 | Հոդված
IEEE Asian Test Symposium (ATS), India, 2011, pp. 461-462
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“Symmetry Measure for Memory Test and Its Application in BIST Optimization”
2011 | Հոդված
Journal of Electronic Testing: Theory and Applications (JETTA), Volume 27, Number 6, December 2011, pp. 753-766
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“TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIODICITY”
2011 | Հոդված
No. 13/183,468, Filing date - July 15, 2011
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“DETECTING RANDOM TELEGRAPH NOISE INDUCED FAILURES IN AN ELECTRONIC MEMORY”
2011 | Հոդված
No. 13/183,471, Filing date - July 15, 2011
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“DETERMINING A DESIRABLE NUMBER OF SEGMENTS FOR A MULTI-SEGMENT SINGLE ERROR CORRECTING CODING SCHEME”
2011 | Հոդված
No. 13/310,479, Filing date – December 2, 2011
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“Minimal Algorithms for Testing Content-Addressable Memories”
2010 |
In proc. of IEEE East-West Design & Test Symposium 2010, St. Petersburg, Russia, September 17-20, 2010
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“Minimal March Test Algorithms for Detection of All Realistic Two-Operation, Two-Cell Dynamic Faults from Subclasses Sav and Sva”
2010 | Հոդված
Reports of National Academy of Sciences of Armenia, 2010, Vol. 110, No. 2, pp. 143-150
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“Fault Location and Diagnosis Algorithm for Static and Dynamic Faults in SRAMs”
2010 | Հոդված
Proceedings of the National Academy of Sciences of Armenia and the State Engineering University of Armenia. Series of Technical Sciences, 2010, Vol. 63, No. 3, pp. 280-287
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“An Efficient March Test for Detection of All Two-Operation Dynamic Faults from Subclass Sav”
2009 | Հոդված
IEEE East-West Design and Test Symposium (EWDTS), Russia, 2009, pp. 175-178
“An Efficient March Test Algorithm for Detection of Resistive Shorts in Multi-Port SRAMs”
2009 | Հոդված
Computer Science and Information Technologies (CSIT), Armenia, 2009, pp. 435-438
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“An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories”
2008 | Հոդված
IEEE VLSI Test Symposium (VTS), USA, 2008, pp. 95 – 100
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“An Efficient Method for Generation of March Tests Based on Formulas”
2008 | Հոդված
Mathematical problems of cybernetics and computer science, Armenia, 2008, pp. 5-17
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“Efficient March-Like Algorithm for Detection of All Two-Operation Dynamic Faults from Subclass Sav”,
2008 | Հոդված
Mathematical problems of cybernetics and computer science, Armenia, 2008, pp. 18-24
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“Minimal March Tests for Detection of Dynamic Faults in Random Access Memories”
2007 | Հոդված
Journal of Electronic Testing: Theory and Applications (JETTA), Volume 23, Number 1, February 2007, pp. 55-74
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"A March-Based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories”
2007 | Հոդված
IEEE Design and Diagnosis of Electronic Circuits and Systems (DDECS), Poland, 2007, pp. 145-148
“Minimal March Tests for Dynamic Faults in Random Access Memories”
2007 | Հոդված
IEEE European Test Symposium (ETS), Germany, 2007, pp. 223 – 227
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“An Efficient 2-Phase March Algorithm for Full Diagnosis of All Simple Static Faults in Random Access Memories”
2007 | Հոդված
IEEE East-West Design and Test Symposium (EWDTS), Armenia, 2007, pp. 110-113
“A Software Tool for Generation of March Algorithms for Faults in SRAMs”
2007 | Հոդված
IEEE East-West Design and Test Symposium (EWDTS), Armenia, 2007, pp. 444-447
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”Minimal March-Based Fault Location Algorithm with Partial Diagnosis for All Static Faults in Random Access Memories”
2006 | Հոդված
IEEE Design and Diagnosis of Electronic Circuits and Systems (DDECS), Czech Republic, 2006, pp. 260-265
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Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories”
2006 | Հոդված
IEEE VLSI Test Symposium (VTS), USA, 2006, pp. 120-125
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“Minimal March Tests for Dynamic Faults in Random Access Memories”
2006 | Հոդված
IEEE European Test Symposium (ETS), UK, 2006, pp. 43-48
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“A March Based Algorithm for Location and Full Diagnosis of All Unlinked Static Faults”
2006 | Հոդված
IEEE Memory Technology, Design and Testing (MTDT), Taiwan, 2006, pp 9-14
“A March Test for Full Diagnosis of All Simple Static Faults in Random Access Memories”
2006 | Հոդված
IEEE East-West Design and Test Workshop (EWDTW), Russia, 2006, pp. 68-71
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“Minimal March Tests for Unlinked Static Faults in Random Access Memories”
2005 | Հոդված
IEEE VLSI Test Symposium (VTS), USA, 2005, pp. 53-59
Minimal March-Based Fault Location Algorithm with Partial Diagnosis for Random Access Memories”
2005 | Հոդված
Computer Science and Information Technologies (CSIT), Armenia, 2005, pp. 519-522