Публикации
Патент
DETECTION OF ADDRESS ERRORS IN MEMORY DEVICES USING MULTI-SEGMENT ERROR DETECTION CODES
2021
Статья
Memory Physical Aware Multi-Level Fault Diagnosis Flow
Статья
Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism
Патент
FINFET-BASED MEMORY TESTING USING MULTIPLE READ OPERATIONS
2019
Статья
Experimental study on Hamming and Hsiao Codes in the Context of Embedded Applications
Статья
Automated Flow for Test Pattern Creation for IPs in SoC
Статья
An Efficient Testing Methodology for Embedded Flash Memories
Статья
Security Issues in Test and Repair Infrastructure for Systems-on-Chip
Патент
Testing Electronic Memories Based on Fault and Test Algorithm Periodicity
2017
Конференция
A power based memory BIST grouping methodology.
2015
27-30
Конференция
Overview study on fault modeling and test methodology development for FinFET-based memories.
2015
19-22
Конференция
Extending fault periodicity table for testing faults in memories under 20nm.
2014
5-9
