Publications
Article
Memory Physical Aware Multi-Level Fault Diagnosis Flow
Article
Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism
Article
Experimental study on Hamming and Hsiao Codes in the Context of Embedded Applications
Article
Automated Flow for Test Pattern Creation for IPs in SoC
Article
An Efficient Testing Methodology for Embedded Flash Memories
Article
Security Issues in Test and Repair Infrastructure for Systems-on-Chip
Conference
Extending fault periodicity table for testing faults in memories under 20nm.
Conference
A power based memory BIST grouping methodology.
Conference
Overview study on fault modeling and test methodology development for FinFET-based memories.
Patent
Testing Electronic Memories Based on Fault and Test Algorithm Periodicity
Patent
FINFET-BASED MEMORY TESTING USING MULTIPLE READ OPERATIONS
Patent
DETECTION OF ADDRESS ERRORS IN MEMORY DEVICES USING MULTI-SEGMENT ERROR DETECTION CODES
