Publications
Patent
DETECTION OF ADDRESS ERRORS IN MEMORY DEVICES USING MULTI-SEGMENT ERROR DETECTION CODES
2021
Article
Memory Physical Aware Multi-Level Fault Diagnosis Flow
Article
Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism
Patent
FINFET-BASED MEMORY TESTING USING MULTIPLE READ OPERATIONS
2019
Article
Experimental study on Hamming and Hsiao Codes in the Context of Embedded Applications
Article
Automated Flow for Test Pattern Creation for IPs in SoC
Article
An Efficient Testing Methodology for Embedded Flash Memories
Article
Security Issues in Test and Repair Infrastructure for Systems-on-Chip
Patent
Testing Electronic Memories Based on Fault and Test Algorithm Periodicity
2017
Conference
A power based memory BIST grouping methodology.
2015
27-30
Conference
Overview study on fault modeling and test methodology development for FinFET-based memories.
2015
19-22
Conference
Extending fault periodicity table for testing faults in memories under 20nm.
2014
5-9
